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? semiconductor components industries, llc, 2013 november, 2013 ? rev. 3 1 publication order number: ncp1937/d ncp1937 combination power factor correction and quasi- resonant flyback controllers for adapters this combination ic integrates power factor correction (pfc) and quasi ? resonant flyback functionality necessary to implement a compact and highly efficient switched mode power supply for an adapter application. the pfc stage exhibits near ? unity power factor while operating in a critical conduction mode (crm) with a maximum frequency clamp. the circuit incorporates all the features necessary for building a robust and compact pfc stage while minimizing the number of external components. the quasi ? resonant current ? mode flyback stage features a proprietary valley ? lockout circuitry, ensuring stable valley switching. this system works down to the 4 th valley and toggles to a frequency foldback mode with a minimum frequency clamp beyond the 4 th valley to eliminate audible noise. skip mode operation allows excellent ef ficiency in light load conditions while consuming very low standby power consumption. common general features ? wide v cc range from 9 v to 30 v with built ? in overvoltage protection ? high ? voltage startup circuit and active input filter capacitor discharge circuitry for reduced standby power ? integrated high ? voltage brown ? out detector ? integrated high ? voltage switch disconnects pfc feedback resistor divider to reduce standby power ? fault input for severe fault conditions, ntc compatible (latch and auto ? recovery options) ? 0.5 a / 0.8 a source / sink gate drivers ? internal temperature shutdown ? power savings mode reduces supply current consumption to 70 a enabling very low input power applications pfc controller features ? critical conduction mode with constant on time control (voltage mode) and maximum frequency clamp ? accurate overvoltage protection ? bi ? level line ? dependent output voltage ? fast line / load transient compensation ? boost diode short ? circuit protection ? feed ? forward for improved operation across line and load ? adjustable pfc disable threshold based on output power qr flyback controller features ? valley switching operation with valley ? lockout for noise ? free operation ? frequency foldback with minimum frequency clamp for highest performance in standby mode ? minimum frequency clamp eliminates audible noise ? timer ? based overload protection (latched or auto ? recovery options) ? adjustable overpower protection ? winding and output diode short ? circuit protection ? 4 ms soft ? start timer http://onsemi.com soic ? 20 narrow body case 751bs marking diagram hv/x2 bo/x2 qfb pcontrol ponoff qct fault pstimer pfbhv pfblv gnd pcs/pzcd pdrv qdrv qcs ncp1937 = specific device code xx = a1, a2, a3, b1, b2, b3, c1, c4 or c61 a = assembly location wl = wafer lot yy = year ww = work week g = pb ? free package 120 ncp1937xxg awlyww vcc qzcd see detailed ordering and shipping information on page 5 of this data sheet. ordering information
ncp1937 http://onsemi.com 2 figure 1. typical application circuit pcs/pzcd vzcd vcc ncp1937 bo/x2 fault pcontrol ponoff pcs/pzcd qzcd qct qcs qfb gnd qdrv pdrv vcc pfblv hv/x2 pfbhv pstimer l psm control n vpstimer n vcc vzcd pcs/pzcd qcs qcs l pdrv pdrv (aux)
ncp1937 http://onsemi.com 3 figure 2. functional block diagram disable pfc pdrv hv/x2 vcc + ? + ? pfbhv + in regulation + timer ? in regulation brownout vcc_ok low/high line puvp pilim1 counter qrdrv qct ct setpoint qzcd leb1 + ? nqilim2 fault ? qfb qcs leb1 leb2 counter frequency clamp leb2 enable bo/x2 high voltage startups, detection, and logic pfblv + ? + ponoff pfc ovp detection qzcd temperature npilim2 pilim2 pskip ? + ? + + ? + + ? + ? 13 qdrv line removal line removal vcc management vcc_ok in psm valley select logic valley qskip vco vco qovld tsd zcd detect valley zcd detect pfcdrv pilim2 pzcd soft ? start central logic reset level shift on time ramp pcontrol low clamp disable pfc puvp povp pzcd pfcdrv s r q dominant reset latch povp low/high line puvp pskip pilim1 pilim2 pfcdrv ovp otp pstimer in psm initial discharge psm detection vcc_ok qrdrv gnd s r q dominant reset latch qilim2 qilim1 qskip qrdrv vcc_ok in psm low/high line s s s s s s qovld npilim2 nqilim2 ovp otp brownout line removal r r r line removal brownout fault logic latch auto ? recovery latch auto ? recovery s tsd qr_en qr_en soft ? start minimum frequency oscillator qrdrv vco pcs/pzcd in_psm i pstimer1/2 v fault(otp_in) i otp v fault(ovp) v pilim2 v pilim1 + ? v ccovp v cc(reset) i pcs/pzcd v pzcd pfcdrv t p(tout) q t pfc(off) v pref(xl) v pcontrol(max) k low k low(hys) pfcdrv v qilim1 pfc i ea v cc(reset) v pfb(hys) v pfb(disable) i pcontrol(boost) k povp(xl) povp(xl) v qilim2 i qcs v qilim1 v qzcd v qzcd t qovld t onqr(max) in_psm i qfb r qfb q v qzcd t q(toutx) v qfb i qct v qzcd(th) v qzcd(hys) qskip t delay(qskip) v qfb soft ? start v poff v ponhys i ponoff c cc i cc(discharge) v ccovp v cc(reset) v dd i start t pisable v qfb /k qfb v pskip 17 10 7 11 14 6 12 1 3 20 18 5 15 16 8 9
ncp1937 http://onsemi.com 4 table 1. pin function description pin out name function 1 hv/x2 high voltage startup circuit input. it is also used to discharge the input filter capacitors. 2 removed for creepage distance. 3 bo/x2 performs brown ? out detection for the whole ic and it is also used to discharge the input filter capacitors and detect the line voltage range. 4 removed for creepage distance. 5 pcontrol output of the pfc transconductance error amplifier. a compensation network is connected between this pin and ground to set the loop bandwidth. 6 ponoff a resistor between this pin and ground sets the pfc turn off threshold. the voltage on this pin is com- pared to an internal voltage signal proportional to the output power. the pfc disable threshold is de- termined by the resistor on this pin and the internal pull?up current source, i ponoff . 7 qct an external capacitor sets the frequency in vco mode for the qr flyback controller. 8 fault the controller enters fault mode if the voltage of this pin is pulled above or below the fault thresholds. a precise pull up current source allows direct interface with an ntc thermistor. fault detection triggers a latch or auto ? recovery depending on device option. 9 pstimer power savings mode (psm) control and timer adjust. compatible with an optocoupler for secondary con- trol of psm. the device enters psm if the voltage on this pin exceeds the psm threshold, v ps_in . a capa- citor between this pin and gnd sets the delay time before the controller enters power savings mode. once the controller enters power savings mode the ic is disabled and the current consumption is re- duced to a maximum of 70 a. the input filter capacitor discharge function is available while in power savings mode. the controller is enabled once v pstimer drops below v ps_out . 10 qfb feedback input for the qr flyback controller. allows direct connection to an optocoupler. 11 qzcd input to the demagnetization detection comparator for the qr flyback controller. also used to set the overpower compensation. 12 vcc supply input. 13 qcs input to the cycle ? by ? cycle current limit comparator for the qr flyback section. 14 qdrv qr flyback controller switch driver. 15 pdrv pfc controller switch driver. 16 pcs/pzcd input to the cycle ? by ? cycle current limit comparator for the pfc section. also used to perform the de- magnetization detection for the pfc controller. 17 gnd ground reference. 18 pfblv low voltage pfc feedback input. an external resistor divider is used to sense the pfc bulk voltage. the divider low side resistor connects to this pin. this voltage is compared to an internal reference. the refer- ence voltage is 2.5 v at low line and 4 v at high line. an internal high ? voltage switch disconnects the low side resistor from the high side resistor chain when the pfc is disabled in order to reduce input power. 19 removed for creepage distance. 20 pfbhv high voltage pfc feedback input. an external resistor divider is used to sense the pfc bulk voltage. the divider high side resistor chain from the pfc bulk voltage connects to this pin. an internal high ? voltage switch disconnects the high side resistor chain from the low side resistor when the pfc is disabled in order to reduce input power.
ncp1937 http://onsemi.com 5 table 2. ncp1937 device options device overload protection fault otp v bo(start) v bo(stop) pfc disable time pfc frequency clamp package shipping ? NCP1937A1DR2G auto ? recovery latch 111 v 97 v 0.5 s 250 khz soic ? 20 (pb ? free) 2500 / tape & reel ncp1937a2dr2g auto ? recovery latch 111 v 97 v 0.5 s 131 khz ncp1937a3dr2g auto ? recovery latch 111 v 97 v 4 s 131 khz ncp1937b1dr2g auto ? recovery auto ? recovery 111 v 97 v 0.5 s 250 khz ncp1937b2dr2g auto ? recovery auto ? recovery 111 v 97 v 0.5 s 131 khz ncp1937b3dr2g auto ? recovery auto ? recovery 111 v 97 v 4 s 131 khz ncp1937c1dr2g latch latch 111 v 97 v 0.5 s 250 khz ncp1937c4dr2g latch latch 111 v 97 v 13 s 131 khz ncp1937c61dr2g latch latch 101 v 87 v 4 s 131 khz ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d. table 3. maximum ratings (notes 1 ? 6) rating pin symbol value unit high voltage startup circuit input voltage 1 v hv/x2 ? 0.3 to 700 v high voltage startup circuit input current 1 i hv/x2 20 ma high voltage brownout detector input voltage 3 v bo/x2 ? 0.3 to 700 v high voltage brownout detector input current 3 i bo/x2 20 ma pfc high voltage feedback input voltage 20 v pfbhv ? 0.3 to 700 v pfc high voltage feedback input current 20 i pfbhv 0.5 ma pfc low voltage feedback input voltage 18 v pfblv ? 0.3 to 9 v pfc low voltage feedback input current 18 i pfblv 0.5 ma pfc zero current detection and current sense input voltage (note 1) 16 v pcs/pzcd ? 0.3 to v pcs/pzcd(max) v pfc zero current detection and current sense input current 16 i pcs/pzcd ? 2/+5 ma pfc control input voltage 5 v pcontrol ? 0.3 to 5 v pfc control input current 5 i pcontrol 10 ma supply input voltage 12 v cc(max) ? 0.3 to 30 v supply input current 12 i cc(max) 30 ma supply input voltage slew rate 12 dv cc /dt 1 v/ s fault input voltage 8 v fault ? 0.3 to (v cc + 1.25) v fault input current 8 i fault 10 ma qr flyback zero current detection input voltage 11 v qzcd ? 0.9 to (v cc + 1.25) v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. v pcs/pzcd(max) is the maximum voltage of the pin shown in the electrical table. when the voltage on this pin exceeds 5 v, the pin sinks a current equal to (v pcs/pzcd ? 5 v) / (2 k ). a v psc/pzcd of 7 v generates a sink current of approximately 1 ma. 2. maximum driver voltage is limited by the driver clamp voltage, v xdrv(high) , when v cc exceeds the driver clamp voltage. otherwise, the maximum driver voltage is v cc . 3. maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyo nd those indicated may adversely affect device reliability. functional operation under absolute maximum?rated conditions is not im plied. functional operation should be restricted to the recommended operating conditions. 4. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. 5. low conductivity board. as mounted on 80 x 100 x 1.5 mm fr4 substrate with a single layer of 50 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec51 ? 1 conductivity test pcb. test conditions were under natural convection of zero air flow. 6. pins 1, 3, and 20 are rated to the maximum voltage of the part, or 700 v.
ncp1937 http://onsemi.com 6 table 3. maximum ratings (notes 1 ? 6) rating unit value symbol pin qr flyback zero current detection input current 11 i qzcd ? 2/+5 ma qr feedback input voltage 7 v qct ? 0.3 to 10 v qr feedback input current 7 i qct 10 ma qr flyback current sense input voltage 13 v qcs ? 0.3 to 10 v qr flyback current sense input current 13 i qcs 10 ma qr flyback feedback input voltage 10 v qfb ? 0.3 to 10 v qr flyback feedback input current 10 i qfb 10 ma pstimer input voltage 9 v pstimer ? 0.3 to 10 v pstimer input current 9 i pstimer 10 ma pfc driver maximum voltage (note 2) 15 v pdrv ? 0.3 to v pdrv(high) v pfc driver maximum current 15 i pdrv(src) i pdrv(snk) 500 800 ma flyback driver maximum voltage (note 2) 14 v qdrv ? 0.3 to v qdrv(high) v flyback driver maximum current 14 i qdrv(src) i qdrv(snk) 500 800 ma pfc on/off threshold adjust input voltage 6 v ponoff ? 0.3 to 10 v pfc on/off threshold adjust input current 6 i ponoff 10 ma operating junction temperature n/a t j ? 40 to 125 c storage temperature range n/a t stg ?60 to 150 c power dissipation (t a = 75 c, 1 oz cu, 0.155 sq inch printed circuit copper clad) plastic package soic ? 20nb p d 0.62 w thermal resistance, junction to ambient 1 oz cu printed circuit copper clad) plastic package soic ? 20nb r ja 121 c/w esd capability (note 6) human body model per jedec standard jesd22 ? a114f. machine model per jedec standard jesd22 ? a115 ? a. charge device model per jedec standard jesd22 ? c101e. hbm mm cdm 3000 200 750 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. v pcs/pzcd(max) is the maximum voltage of the pin shown in the electrical table. when the voltage on this pin exceeds 5 v, the pin sinks a current equal to (v pcs/pzcd ? 5 v) / (2 k ). a v psc/pzcd of 7 v generates a sink current of approximately 1 ma. 2. maximum driver voltage is limited by the driver clamp voltage, v xdrv(high) , when v cc exceeds the driver clamp voltage. otherwise, the maximum driver voltage is v cc . 3. maximum ratings are those values beyond which damage to the device may occur. exposure to these conditions or conditions beyo nd those indicated may adversely affect device reliability. functional operation under absolute maximum?rated conditions is not im plied. functional operation should be restricted to the recommended operating conditions. 4. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78. 5. low conductivity board. as mounted on 80 x 100 x 1.5 mm fr4 substrate with a single layer of 50 mm 2 of 2 oz copper traces and heat spreading area. as specified for a jedec51 ? 1 conductivity test pcb. test conditions were under natural convection of zero air flow. 6. pins 1, 3, and 20 are rated to the maximum voltage of the part, or 700 v.
ncp1937 http://onsemi.com 7 table 4. electrical characteristics: (v cc = 12 v, v bo/x2 = 120 v, v hv/x2 = 120 v, v fault = open, v rpfbhv = 20 v, v pfblv = 2.4 v, v pcontrol = 4 v, v pcs/pzcd = 0 v, v qfb = 3 v, v ponoff = 4 v, v qcs = 0 v, v qzcd = 0 v, v pstimer = 0 v, r pfbhv = 200 k , c vcc = 100 nf , c qct = 220 pf, c pdrv = 1 nf, c qdrv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics conditions pin symbol min typ max unit startup and supply circuits supply voltage startup threshold regulation level in psm minimum operating voltage operating hysteresis delta between psm and v cc(off) levels internal latch / logic reset level transition from i start1 to i start2 v cc increasing v qfb = 0, v pstimer = 3 v v cc decreasing v cc(on) ? v cc(off) v cc(ps_on) ? v cc(off) v cc decreasing v cc increasing, i hv/x2 = 650 a 12 v cc(on) v cc(ps_on) v cc(off) v cc(hys) v cc( ps_off) v cc(reset) v cc(inhibit) 16 ? 8.2 7.7 1.65 4.5 0.3 17 11 8.8 ? 2.20 5.5 0.7 18 ? 9.4 ? 2.75 7.5 0.95 v startup current in inhibit mode v cc = 0 v, v bo/x2 = 0 v v cc = 0 v, v hv/x2 = 0 v 12 12 i start1a i start1b 0.20 0.20 0.50 0.50 0.65 0.65 ma startup current operating mode psm mode v cc = v cc(on) ? 0.5 v v hv/x2 = 100 v, v bo/x2 = v cc v bo/x2 = 100 v, v hv/x2 = v cc v hv/x2 = 100 v, v bo/x2 = 0 v v bo/x2 = 100 v, v hv/x2 = 0 v 12 12 i start2a i start2b i start2a_psm i start2b_psm 2.5 2.5 9 9 15 15 5 5 20 20 ma startup circuit off ? state leakage current v hv/x2 = 500 v 1 i hv/x2 (off) ? ? 3 a minimum startup voltage i start2a = 1 ma, v cc = v cc(on) ? 0.5 v i start2b = 1 ma, v cc = v cc(on) ? 0.5 v 1 3 v hv/x2(min) v bo/x2(min) ? ? ? ? 40 40 v minimum startup voltage in psm i start = 9 ma, v cc = v cc(ps_on) ? 0.5 v i start = 9 ma, v cc = v cc(ps_on) ? 0.5 v 1 3 v hv/x2(min) v bo/x2(min) ? ? ? ? 60 60 v v cc overvoltage protection threshold 12 v cc(ovp) 27 28 29 v v cc overvoltage protection delay 12 t delay(vcc_ovp) 30.0 s supply current in power savings mode before startup, fault or latch flyback in skip, pfc disabled flyback in skip, pfc in skip flyback enabled, qdrv low, pfc disabled flyback enabled, qdrv low, pfc in skip pfc and flyback switching at 70 khz pfc and flyback switching at 70 khz v cc = v cc(on) ? 0.5 v v qfb = 0.35 v v qfb = 0.35 v, v pcontrol < v pskip v qzcd = 1 v, v qzcd = 1 v, v pcontrol < v pskip c qdrv = c pdrv = open 12 i cc1a i cc2 i cc3a i cc3b i cc4 i cc5 i cc6 i cc7 ? ? 0.15 0.3 0.5 0.85 1.1 1.5 2.8 0.07 0.25 0.4 1.0 1.35 1.8 4.0 5.2 ma input filter discharge current consumption in discharge mode v cc = v cc(off) + 200 mv 12 i cc(discharge) 8.0 11.5 15.0 ma line voltage removal detection threshold v bo/x2 decreasing 3 v lineremoval 20 30 40 v line voltage removal detection delay v bo/x2 stays above v lineremoval 3 t lineremoval 130 200 270 ms
ncp1937 http://onsemi.com 8 table 4. electrical characteristics: (v cc = 12 v, v bo/x2 = 120 v, v hv/x2 = 120 v, v fault = open, v rpfbhv = 20 v, v pfblv = 2.4 v, v pcontrol = 4 v, v pcs/pzcd = 0 v, v qfb = 3 v, v ponoff = 4 v, v qcs = 0 v, v qzcd = 0 v, v pstimer = 0 v, r pfbhv = 200 k , c vcc = 100 nf , c qct = 220 pf, c pdrv = 1 nf, c qdrv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol pin conditions brown ? out detection system brown ? out thresholds (see table 2 for device options) v bo/x2 increasing v bo/x2 decreasing 3 v bo(start) v bo(stop) 102 86 111 101 120 116 v system brown ? out thresholds (see table 2 for device options) v bo/x2 increasing v bo/x2 decreasing 3 v bo(start) v bo(stop) 83 79 97 87 111 95 v brown ? out hysteresis v bo/x2 increasing 3 v bo(hys) 4 16 v brown ? out detection blanking time v bo/x2 decreasing, duration below v bo(stop) for a brown ? out fault 3 t bo(stop) 43 54 65 ms brown ? out drive disable threshold v bo/x2 decreasing, threshold to disable switching 3 v bo(drv_disable) 20 30 40 v line level detection threshold line level detection threshold (c61) v bo/x2 increasing 3 v bo(lineselect) 216 199 240 221 264 243 v high to low line mode selector timer v bo/x2 decreasing 3 t high to low line 43 54 65 ms low to high line mode selector timer v bo/x2 increasing 3 t low to high line 200 350 450 s brownout pin off state leakage current v bo/x2 = 500 v 3 i bo/x2(off) ? ? 42 a pfc maximum off time timer maximum off time v pcs/pzcd > v pilim2 15 t pfc(off1) t pfc(off2) 100 700 200 1000 300 1300 s pfc current sense cycle by cycle current sense threshold 16 v pilim1 0.45 0.50 0.55 v cycle by cycle leading edge blanking duration 16 t pcs(leb1) 250 325 400 ns cycle by cycle current sense propagation delay 16 t pcs(delay1) 100 200 ns abnormal overcurrent fault threshold 16 v pilim2 1.12 1.25 1.38 v abnormal overcurrent fault leading edge blanking duration 16 t pcs(leb2) 100 175 250 ns abnormal overcurrent fault propagation delay 16 t pcs(delay2) 100 200 ns number of consecutive abnormal overcurrent faults to enter latch mode 15 n pilim2 ? 4 ? pull ? up current source v pcs/pzcd = 1.5 v 16 i pcs/pzcd 0.7 1.0 1.3 a pfc regulation block reference voltage v bo/x2 > v bo(lineselect) v bo/x2 < v bo(lineselect) 18 v pref(hl) v pref(ll) 3.92 2.45 4.00 2.50 4.08 2.55 v error amplifier current source sink source sink pfc enabled v pfblv = 0.96 x v pref(hl) v pfblv = 1.04 x v pref(hl) v pfblv = 0.96 x v pref(ll) v pfblv = 1.04 x v pref(ll) 5 i ea(srchl) i ea(snkhl) i ea(srcll) i ea(snkll) 16 16 10 10 32 32 20 20 48 48 30 30 a open loop error amplifier transconductance v pfblv = v pref(ll) 4% v pfblv = v pref(hl) 4% 5 g m g m_hl 100 100 200 200 300 300 s maximum control voltage v pfblv * k low(pfcxl) , c pcontrol = 10 nf 5 v pcontrol(max) ? 4.5 ? v minimum control voltage (pwm offset) v pfblv * k povp(xl) , c pcontrol = 10 nf 5 v pcontrol(min) ? 0.5 ? v
ncp1937 http://onsemi.com 9 table 4. electrical characteristics: (v cc = 12 v, v bo/x2 = 120 v, v hv/x2 = 120 v, v fault = open, v rpfbhv = 20 v, v pfblv = 2.4 v, v pcontrol = 4 v, v pcs/pzcd = 0 v, v qfb = 3 v, v ponoff = 4 v, v qcs = 0 v, v qzcd = 0 v, v pstimer = 0 v, r pfbhv = 200 k , c vcc = 100 nf , c qct = 220 pf, c pdrv = 1 nf, c qdrv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol pin conditions pfc regulation block ea output control voltage range v pcontrol(max) - v pcontrol(min) 5 v pcontrol 3.8 4.0 4.2 v delta between minimum control voltage and lower clamp pcontrol voltages v pcontrol(min) ? v pclamp(lower) 5 v pclamp(lower) ? 125 ? 100 ? 75 mv ratio between the v out low detect threshold and the regulation level v pfblv decreasing, v boost / v pref(hl) v pfblv decreasing, v boost / v pref(ll) 18 k low(pfchl) k low(pfcll) 0.940 0.940 0.945 0.945 0.950 0.950 ratio between the v out low exit threshold and the regulation level v pfblv increasing 18 k low(hyshl) k low(hysll) 0.950 0.950 0.960 0.960 0.965 0.965 source current during v out low detect 5 i pcontrol(boost) 190 240 290 a pfc in regulation threshold v pcontrol increasing 5 i in_regulation ? 6.5 ? 0 a resistance of internal pull down switch i pcontrol = 5 ma 5 r pcontrol 4 25 50 pfc skip mode delta between skip level and lower clamp pcontrol voltages v pcontrol decreasing, measured from v pclamp(lower) 5 v pskip 5 25 50 mv pfc skip hysteresis v pcontrol increasing 5 v pskip(hys) 25 50 75 mv delay exiting skip mode apply 1 v step from v pclamp(lower) 5 t delay(pskip) ? 50 60 s pfc fault protection ratio between the hard overvoltage pro- tection threshold and regulation level v pfblv increasing k povp(ll) = v pfblv /v pref(ll) k povp(hl) = v pfblv /v pref(hl) 18 k povp(ll) k povp(hl) 1.06 1.05 1.08 1.06 1.10 1.08 soft overvoltage protection threshold v psovp(ll) = soft overvoltage level povp(ll) = k povp * v pref(ll) ? v psovp(ll) povp(hl) = k povp * v pref(hl) ? v psovp(hl) 18 povp(ll) povp(hl) 20 20 ? ? 55 55 mv pfc feedback pin disable threshold v pfblv decreasing 18 v pfb(disable) 0.225 0.30 0.35 v pfc feedback pin enable threshold v pfblv increasing 18 v pfb(enable) 0.275 0.35 0.40 v pfc feedback pin hysteresis v pfblv increasing 18 v pfb(hys) 25 50 mv pfc feedback disable delay 18 t delay(pfb) 30 s pfc on time control pfc maximum on time v pcontrol = v pcontrol(max) , v bo/x2 = 163 v v bo/x2 = 325 v 15 t on1a t on1b 12.5 4.25 15 5.00 17.5 5.75 s minimum on ? time v pcontrol = v pcontrol(min) 15 t p(on ? time) ? ? 200 ns pfc frequency clamp (see table 2 for device options) 15 f clamp(pfc) 112 215 131 250 150 285 khz
ncp1937 http://onsemi.com 10 table 4. electrical characteristics: (v cc = 12 v, v bo/x2 = 120 v, v hv/x2 = 120 v, v fault = open, v rpfbhv = 20 v, v pfblv = 2.4 v, v pcontrol = 4 v, v pcs/pzcd = 0 v, v qfb = 3 v, v ponoff = 4 v, v qcs = 0 v, v qzcd = 0 v, v pstimer = 0 v, r pfbhv = 200 k , c vcc = 100 nf , c qct = 220 pf, c pdrv = 1 nf, c qdrv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol pin conditions pfc disable voltage to current conversion ratio v qfb = 3 v, low line v qfb = 3 v, high line 6 i ratio1(qfb/pon) i ratio2(qfb/pon) 14 14 15 15 16 16 a pfc disable threshold v ponoff decreasing 6 v poff 1.9 2.0 2.1 v pfc enable hysteresis v ponoff = increasing 6 v ponhys 0.135 0.160 0.185 v ponoff operating mode voltage t demag /t = 70%, r ponoff = 191 k , c ponoff = 1 nf v qfb = 1.8 v (decreasing) v qfb = 3 v (decreasing) 6 v ponoff1 v ponoff2 1.08 1.8 1.20 2.0 1.32 2.2 v pfc disable timer (see table 2 for device options) disable timer 6 t pdisable 0.45 3.6 11.7 0.50 4 13 0.55 4.4 14.3 s pfc enable filter delay 6 t penable(filter) 50 100 150 s pfc enable timer ponoff increasing 6 t penable 200 ? 500 s pfc off ? state leakage current v ponoff = 1 v, v pfbhv = 500 v 20 i pfbhv(off) ? 0.1 3 a pfc feedback switch on resistance v pfbhv = 4.25 v, i pfbhv = 100 a 20 r pfbswitch(on) ? ? 10 k pfc gate drive rise time (10 ? 90%) v pdrv from 10 to 90% of v cc 15 t pdrv(rise) ? 40 80 ns fall time (90 ? 10%) 90 to 10% of v pdrv 15 t pdrv(fall) ? 20 40 ns driver resistance source sink 15 r pdrv(src) r pdrv(snk) 13 7 current capability source sink v pdrv = 2 v v pdrv = 10 v 15 i pdrv(src) i pdrv(snk) ? ? 500 800 ? ? ma high state voltage v cc = v cc(off) + 0.2 v, r pdrv = 10 k v cc = 26 v, r pdrv = 10 k 15 v pdrv(high) 8 10 ? 12 ? 14 v low stage voltage v fault = 4 v 15 v pdrv(low) ? ? 0.25 v pfc zero current detection zero current detection threshold v pcs/pzcd rising v pcs/pzcd falling 16 v pzcd(rising) v pzcd(falling) 675 200 750 250 825 300 mv hysteresis on voltage threshold v pzcd(rising) ? v pzcd(falling) 16 v p zcd(hys) 375 500 625 mv propagation delay 16 t pzcd 50 100 170 ns input voltage excursion upper clamp negative clamp i pcs/pzcd = 1 ma i pcs/pzcd = ? 2 ma 16 v pcs/pzcd(max) v pcs/pzcd(min) 6.5 ? 0.9 7 ? 0.7 7.5 0 v minimum detectable zcd pulse width 16 t sync ? 70 200 ns missing valley timeout timer measured after last zcd transition 16 t p(tout) 8 10 12 s
ncp1937 http://onsemi.com 11 table 4. electrical characteristics: (v cc = 12 v, v bo/x2 = 120 v, v hv/x2 = 120 v, v fault = open, v rpfbhv = 20 v, v pfblv = 2.4 v, v pcontrol = 4 v, v pcs/pzcd = 0 v, v qfb = 3 v, v ponoff = 4 v, v qcs = 0 v, v qzcd = 0 v, v pstimer = 0 v, r pfbhv = 200 k , c vcc = 100 nf , c qct = 220 pf, c pdrv = 1 nf, c qdrv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol pin conditions qr flyback gate drive rise time (10 ? 90%) v qdrv from 10 to 90% 14 t qdrv(rise) ? 40 80 ns fall time (90 ? 10%) 90 to 10% of v qdrv 14 t qdrv(fall) ? 20 40 ns driver resistance source sink 14 r qdrv(src) r qdrv(snk) 13 7 current capability source sink v qdrv = 2 v v qdrv = 10 v 14 i qdrv(src) i qdrv(snk) ? ? 500 800 ? ? ma high state voltage v cc = v cc(off) + 0.2 v, r qdrv = 10 k v cc = 26 v, r qdrv = 10 k 14 v qdrv(high) 8 10 ? 12 ? 14 v low stage voltage v fault = 4 v 14 v qdrv(low) ? ? 0.25 v qr flyback feedback internal pull ? up current source 10 i qfb 46.75 50 53.25 a feedback input open voltage 10 v qfb(open) 4.5 5.0 5.5 v v qfb to internal current setpoint division ratio 10 k qfb 3.8 4.0 4.2 ? qfb pull up resistor v pstimer = 3 v; v qfb = 0.4 v 10 r qfb 340 400 460 k valley thresholds transition from 1 st to 2 nd valley transition from 2 nd to 3 rd valley transition from 3 rd to 4 th valley transition from 4 th valley to vco transition from vco to 4 th valley transition from 4 th to 3 rd valley transition from 3 rd to 2 nd valley transition from 2 nd to 1 st valley v qfb decreasing v qfb decreasing v qfb decreasing v qfb decreasing v qfb increasing v qfb increasing v qfb increasing v qfb increasing 10 v h2d v h3d v h4d v hvcod v hvcoi v h4i v h3i v h2i 1.316 1.128 0.846 0.752 1.316 1.504 1.692 1.880 1.400 1.200 0.900 0.800 1.400 1.600 1.800 2.000 1.484 1.272 0.954 0.848 1.484 1.696 1.908 2.120 v skip threshold v qfb decreasing 10 v qskip 0.35 0.40 0.45 v skip hysteresis v qfb increasing 10 v qskip(hys) 25 50 75 mv delay exiting skip mode to 1 st qdrv pulse apply 1 v step from v qskip 10 t delay(qskip) ? ? 10 s maximum on time 14 t onqr(max) 26 32 38 s qr flyback timing capacitor qct operating voltage range v qfb = 0.5 v 7 v qct(peak) 3.815 4.000 4.185 v on time control source current v qct = 0 v 7 i qct 18 20 22 a minimum voltage on qct input 7 v qct(min) ? ? 90 mv minimum operating frequency in vco mode v qct = v qct(peak) + 100 mv 7 f vco(min) 23.5 27 30.5 khz
ncp1937 http://onsemi.com 12 table 4. electrical characteristics: (v cc = 12 v, v bo/x2 = 120 v, v hv/x2 = 120 v, v fault = open, v rpfbhv = 20 v, v pfblv = 2.4 v, v pcontrol = 4 v, v pcs/pzcd = 0 v, v qfb = 3 v, v ponoff = 4 v, v qcs = 0 v, v qzcd = 0 v, v pstimer = 0 v, r pfbhv = 200 k , c vcc = 100 nf , c qct = 220 pf, c pdrv = 1 nf, c qdrv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol pin conditions qr flyback demagnetization input qzcd threshold voltage v qzcd decreasing 11 v qzcd(th) 35 55 90 mv qzcd hysteresis v qzcd increasing 11 v qzcd(hys) 15 35 55 mv demagnetization propagation delay v qzcd step from 4.0 v to ? 0.3 v 11 t dem ? 150 250 ns input voltage excursion upper clamp negative clamp i qzcd = 5.0 ma i qzcd = ? 2.0 ma 11 v qzcd(max) v qzcd(min) 12.4 ? 0.9 12.7 ? 0.7 13.25 0 v blanking delay after turn ? off 11 t zcd(blank) 2 3 4 s timeout after last demagnetization detection during soft ? start after soft ? start 14 t q(tout1) t q(tout2) 80 5.1 100 6 120 6.9 s qr flyback current sense current sense voltage threshold v qcs increasing v qcs increasing, v qzcd = 1 v 13 v qilim1a v qilim1b 0.760 0.760 0.800 0.800 0.840 0.840 v cycle by cycle leading edge blanking duration 13 t qcs(leb1) 220 275 350 ns cycle by cycle current sense propagation delay 13 t qcs(delay1) ? 125 175 ns immediate fault protection threshold v qcs increasing, v qfb = 4 v 13 v qilim2 1.125 1.200 1.275 v abnormal overcurrent fault leading edge blanking duration 13 t qcs(leb2) 90 120 150 ns abnormal overcurrent fault propagation delay 13 t qcs(delay2) ? 125 175 ns number of consecutive abnormal overcurrent faults to enter latch mode 13 n qilim2 ? 4 ? minimum peak current level in vco mode v qfb = 0.4 v, v qcs increasing 13 i peak(vco) 11 12.5 14 % set point decrease for v qzcd = ? 250 mv v qcs increasing, v qfb = 4 v 13 v opp(max) 28 31.25 33 % overpower protection delay 11 t qopp(delay) ? 125 175 ns pull ? up current source v qcs = 1.5 v 13 i qcs 0.7 1.0 1.3 a qr flyback fault protection soft ? start period 13 t sstart 2.8 4.0 5.0 ms flyback overload fault timer v qcs = v qilim1 13 t qovld 60 80 100 ms
ncp1937 http://onsemi.com 13 table 4. electrical characteristics: (v cc = 12 v, v bo/x2 = 120 v, v hv/x2 = 120 v, v fault = open, v rpfbhv = 20 v, v pfblv = 2.4 v, v pcontrol = 4 v, v pcs/pzcd = 0 v, v qfb = 3 v, v ponoff = 4 v, v qcs = 0 v, v qzcd = 0 v, v pstimer = 0 v, r pfbhv = 200 k , c vcc = 100 nf , c qct = 220 pf, c pdrv = 1 nf, c qdrv = 1 nf, for typical values t j = 25 c, for min/max values, t j is ? 40 c to 125 c, unless otherwise noted) characteristics unit max typ min symbol pin conditions common fault protection overvoltage protection (ovp) threshold v fault increasing 8 v fault(ovp) 2.79 3.00 3.21 v delay before fault confirmation used for ovp detection used for otp detection v fault increasing v fault decreasing 8 t delay(fault_ovp) t delay(fault_otp) 22.5 22.5 30.0 30.0 37.5 37.5 s overtemperature protection (otp) threshold (note 7) v fault decreasing 8 v fault(otp_in) 0.38 0.40 0.42 v overtemperature protection (otp) exiting threshold (note 7) v fault increasing, options b and d 8 v fault(otp_out) 0.874 0.920 0.966 v otp pull ? up current source (note 7) v fault = v fault(otp_in) + 0.2 v t j = 110 c 8 i fault(otp) i fault(otp_110) 42.5 ? 45.5 45.5 48.5 ? a fault input clamp voltage v fault = open 8 v fault(clamp) 1.5 1.75 2.0 v fault input clamp series resistor r fault(clamp) 1.32 1.55 1.82 k power savings mode psm enable threshold v pstimer increasing 9 v ps_in 3.325 3.500 3.675 v psm disable threshold v pstimer decreasing 9 v ps_out 0.45 0.50 0.55 v pstimer pull up current sources v pstimer = 0.9 v v pstimer = 3.4 v 9 i pstimer1 i pstimer2 9 800 10 1000 11 1200 a i pstimer2 enable threshold 9 v pstimer2 0.95 1.0 1.05 v filter delay before entering psm 9 t delay(ps_in) 40 s startup circuits turn ? on thresholds in psm v hv_x2 increasing v bo_x2 increasing 1 3 v hv_x2(ps) v bo_x2(ps) 20 20 30 30 40 40 v pstimer discharge current v pstimer = v pstimer(off) + 10 mv 9 i pstimer(dis) 200 ? ? a pstimer discharge turn off threshold v pstimer decreasing 9 v pstimer(off) 50 100 150 mv thermal protection thermal shutdown temperature increasing n/a t shdn 150 c thermal shutdown hysteresis temperature decreasing n/a t shdn(hys) 40 c 7. ntc with r 110 = 8.8 k (ttc03 ? 474)
ncp1937 http://onsemi.com 14 detailed operating description introduction the ncp1937 is a combination critical mode (crm) power factor correction (pfc) and quasi ? resonant (qr) flyback controller optimized for off ? line adapter applications. this device includes all the features needed to implement a highly efficient adapter with extremely low input power in no ? load conditions. this device reduces standby input power by integrating an active input filter capacitor discharge circuit and disconnecting the pfc feedback resistor divider when the pfc is disabled. high voltage startup circuit the ncp1937 integrates two high voltage startup circuits accessible by the hv_x2 and bo_x2 pins. the startup circuits are also used for input filter capacitor discharge. the bo_x2 input is also used for monitoring the ac line voltage and detecting brown ? out faults. the startup circuits are rated at a maximum voltage of 700 v. a startup regulator consists of a constant current source that supplies current from the ac input terminals (v in ) to the supply capacitor on the v cc pin (c cc ). the startup circuit currents (i start2a/b ) are typically 3.75 ma. i start2a/b are disabled if the vcc pin is below v cc(inhibit) . in this condition the startup current is reduced to i start1a/b , typically 0.5 ma. the internal high voltage startup circuits eliminate the need for external startup components. in addition, these regulators reduce no load power and increase the system efficiency as they use negligible power in the normal operation mode. once c cc is charged to the startup threshold, v cc(on) , typically 17 v, the startup regulators are disabled and the controller is enabled. the startup regulators remain disabled until v cc falls below the minimum operating voltage threshold, v cc(off) , typically 8.8 v. once reached, the pfc and flyback controllers are disabled reducing the bias current consumption of the ic. both startup circuits are then enabled allowing v cc to charge back up. in power savings mode v cc is regulated by enabling the startup circuits once the supply voltage decays below v cc(ps_on) , typically 11 v. the startup circuit is disabled once v cc exceeds v cc(ps_on) . this provides enough headroom from v cc(off) to maintain a supply voltage and allow the controller to detect the line voltage removal in order to discharge the input filter capacitor(s). in this mode, the supply capacitor is charged by the startup circuit on the hv_x2 and bo_x2 pins once the voltage on these pin exceeds 30 v, typically. this reduces the average voltage during which the startup circuit is enabled reducing power consumption. both startup circuits are enabled once the controller exits power savings mode in order to quickly charge v cc . a new startup sequence commences once v cc reaches v cc(on) . a dedicated comparator monitors v cc when the qr stage is enabled and latches off the controller if v cc exceeds v cc(ovp) , typically 28 v. the controller is disabled once a fault is detected. the controller will restart the next time v cc reaches v cc(on) and all non ? latching faults have been removed. the supply capacitor provides power to the controller during power up. the capacitor must be sized such that a v cc voltage greater than v cc(off) is maintained while the auxiliary supply voltage is building up. otherwise, v cc will collapse and the controller will turn off. the operating ic bias current, i cc4 , and gate charge load at the drive outputs must be considered to correctly size c cc . the increase in current consumption due to external gate charge is calculated using equation 1. i cc(gate charge) f q g (eq. 1) where f is the operating frequency and q g is the gate charge of the external mosfets. line voltage sense the bo/x2 pin provides access to the brown ? out and line voltage detectors. it also provides access to the input filter capacitor discharge circuit. the brown ? out detector detects mains interruptions and the line voltage detector determines the presence of either 110 v or 220 v ac mains. depending on the detected input voltage range device parameters are internally adjusted to optimize the system performance. this pin connects to either line or neutral to achieve half ? wave rectification as shown in figure 3. a diode is used to prevent the pin from going below ground. a resistor in series with the bo/x2 pin can be used for protection, but a low value (< 3 k ) resistor should be used to reduce the voltage offset while sensing the line voltage. figure 3. brown ? out and line voltage detectors configuration the flyback stage is enabled once v bo_x2 is above the brown ? out threshold, v bo(start) , and v cc reaches v cc(on) . the high voltage startups are immediately enabled when the voltage on v bo_x2 crosses over the brown ? out start threshold, v bo(start), to ensure that device is enabled quickly upon exiting a brown ? out state. figure 4 shows typical power up waveforms.
ncp1937 http://onsemi.com 15 time time vcc time qdrv startup startup startup turns on when device exits a brown ? out figure 4. startup timing diagram v bo_x2 v bo(start) v bo/x2(min) v cc(on) v cc(off) v cc(inhibit) current = i start1 current = i start2 a timer is enabled once v bo_x2 drops below its stop threshold, v bo(stop) . if the timer, t bo , expires the device will begin monitoring the voltage on v bo_x2 and disable the pfc and flyback stages when that voltage is below the brown ? out drive disable threshold, v bo(drv_disable), typically 30 v. this ensures that device switching is stopped in a low energy state which minimizes inductive voltage kick from the emi components and ac mains. the timer, t bo , typically 54 ms, is set long enough to ignore a single cycle drop ? out. line voltage detector the input voltage range is detected based on the peak voltage measured at the bo_x2 pin. discrete values are selected for the pfc stage gain (feedforward) depending on the input voltage range. the controller compares v bo_x2 to an internal line select threshold, v bo(lineselect) . once v bo_x2 exceeds v bo(lineselect) , the pfc stage operates in ?high line? (europe/asia) or ?220 vac? mode. in high line mode the maximum on time is reduced by a factor of 3, resulting in a maximum output power independent of input voltage. figure 5 shows typical operation for the line voltage detector. the default power ? up mode of the controller is low line. the controller switches to ?high line? mode if v bo_x2 exceeds the line select threshold for longer than the low to high line timer, t (low to high line) , typically 300 s, as long as it was not previously in high line mode. if the controller has switched from ?high line? to ?low line? mode, the low to high line timer, t (low to high line) , is inhibited until v bo/x2 falls below v bo(stop) . this prevents the controller from toggling back to ?high line? until at least one v bo(stop) transition has occurred. the timer and logic is included to prevent unwanted noise from toggling the operating line level. in ?high line? mode the high to low line timer, t (high to low line) , (typically 54 ms) is enabled once v bo_x2 falls below v bo(lineselect) . it is reset once v bo_x2 exceeds v bo(lineselect) . the controller switches back to ?low line? mode if the high to low line timer expires.
ncp1937 http://onsemi.com 16 time high line entered hl transition blanked by t low to high line t (high to low line) line timer reset line timer starts line timer starts low line entered line timer expires t (low to high line ) time high line low line v bo/x2 low line low line select timer operating mode time transition to high line allowed? yes no yes hl transition blanked by v bo(stop) counter v bo(stop) figure 5. line detector waveforms v bo(lineselect) input filter capacitor discharge safety agency standards require the input filter capacitors to be discharged once the ac line voltage is removed. a resistor network is the most common method to meet this requirement. unfortunately, the resistor network consumes power across all operating modes and is a major contributor to the total input power dissipation during light ? load and no ? load conditions. the ncp1937 eliminates the need for external discharge resistors by integrating active input filter capacitor discharge circuitry. a novel approach is used to reconfigure the high voltage startup circuits to discharge the input filter capacitors upon removal of the ac line voltage. once the controller detects the absence of the ac line voltage, the controller is disabled and v cc is discharged by a current source, i cc(discharge) , typically 11.5 ma. this will cause v cc to fall down to v cc(off) . upon reaching v cc(off) , both startup circuits are enabled. the startup circuits will then source current from the bo_x2 and hv_x2 inputs to the vcc pin and discharge the input filter capacitors by transferring its charge to the v cc capacitor(s). the input filter capacitor(s) are typically discharged once the startup circuit turns on the 1 st time because the energy stored in the input filter capacitor(s) is significantly lower than the energy needed to charge the v cc capacitor from v cc(off) to v cc(on) . after the initial discharge the controller enters a low current mode (i cc2 ) once v cc drops to v cc(off) . in the event that the input filter capacitor is not fully discharged, a larger v cc capacitor should be used. but, this is not a concern for most applications because the supply capacitor value will be large enough to maintain v cc during skip operation. figure 6 shows typical behavior of the filter capacitor discharge when the ac line is removed.
ncp1937 http://onsemi.com 17 figure 6. input filter capacitor discharge waveforms qdrv hv startups turn on ac mains unplugged 0 v input filter cap discharged v cc(off) v cc v ac i cc(discharge) begins t lineremoval the diode connecting the ac line to the bo_x2 pin should be placed after the system fuse. a resistor in series with the bo_x2 pin is recommended to limit the current during transient events. a low value resistor (< 3 k ) should be used to reduce the voltage drop when the startup circuit is enabled. power savings mode the ncp1937 has a low current consumption mode known as power savings mode (psm). the supply current consumption in this mode is below 70 a. psm operation is controlled by an external control signal. this signal is typically generated on the secondary side of the power supply and fed via an optocoupler. the ncp1937 is configured as active on logic, that is it enters psm in the absence of the control signal. the control signal is applied to the pstimer pin. the block diagram for ncp1937 pst imer pin is shown in figure 7. power savings mode operating waveforms for the ncp1937 are shown in figure 8. the ncp1937 controller starts once v cc reaches v cc(on) and no faults are present. at this time the current source on the pstimer pin, i pstimer1 , is enabled. i pstimer1 is typically 10 a. the current source charges the capacitor connected from this pin to ground. once v pstimer reaches v pstimer2 a 2 nd current source, i pstimer2 , is enabled to speed up the charge of c psm . v pstimer2 and i pstimer2 are typically 1 v and 1 ma, respectively. the controller enters psm if the voltage on v pstimer exceeds v ps_in , typically 3.5 v. an external optocoupler or switch needs to pull down on this pin before its voltage reaches v ps_in to prevent entering psm. once the controller enters psm, i pstimer1/2 is disabled. a resistor between this pin and ground discharges the pst imer capacitor. the controller exits psm once v pstimer drops below v ps_out , typically 0.5 v. once the qr stage is enabled, the capacitor on the pstimer pin is discharged with an internal pull down transistor. the transistor is disabled once v pstimer falls below its minimum operating level, v pstimer(min) (maximum of 50 mv). the time to enter psm mode is calculated using equations 2 through 4. the time to exit psm mode is calculated using equation 5. t psm(in) t psm(in1) t psm(in2) (eq. 2) t psm(in1) ? r psm c psm in 1 ? v pstimer2 i pstimer1 r psm (eq. 3) t psm(in2) ? r psm c psm in 1 ? v ps_in ? v pstimer2 i pstimer2 r psm (eq. 4) t psm(out) ? r psm c psm in v ps_out v ps_in (eq. 5) in psm the startup circuits on the hv_x2 and bo_x2 pins work to maintain v cc above v cc(off) . the input filter capacitor discharge circuitry continues operation in psm. the supply voltage is maintained in psm by enabling one of the startup circuits once v cc falls below v cc(ps_on) (typically 11 v) and either v hv_x2 exceeds v hv_x2(ps) or v bo_x2 exceeds v bo_x2(ps) (typically 30 v). the startup circuit is disabled once v cc exceeds v cc(ps_on) . a voltage offset is observed on v cc while the startup circuit is enabled due to the capacitor esr. this will cause the startup circuit to turn off because v cc exceeds v cc(ps_on) . internal circuitry prevents the startup circuit from turning on multiple times during the same ac line half ? cycle. the complementary startup circuit will then turn on during the next half ? cycle. eventually, v cc will be regulated several millivolts below v cc(ps_on) . the offset is dependent on the capacitor esr. this architecture enables the startup circuit for the exact amount of time needed to regulate v cc . this results in a significant reduction in power dissipation because the average input voltage is greatly reduced.
ncp1937 http://onsemi.com 18 figure 7. ncp1937 power savings mode control block diagram figure 8. ncp1937 power savings mode operating waveforms
ncp1937 http://onsemi.com 19 fault input the ncp1937 includes a dedicated fault input accessible via the fault pin. the controller can be latched by pulling the pin above the upper fault threshold, v fault(ovp) , typically 3.0 v. the controller is disabled if the fault pin voltage, v fault , is pulled below the lower fault threshold, v fault(otp_in) , typically 0.4 v. the lower threshold is normally used for detecting an overtemperature fault. the controller operates normally while the fault pin voltage is maintained within the upper and lower fault thresholds. figure 9 shows the architecture of the fault input. the lower fault threshold is intended to be used to detect an overtemperature fault using an ntc thermistor. a pull up current source i fault(otp) , (typically 45.5 a) generates a voltage drop across the thermistor. the resistance of the ntc thermistor decreases at higher temperatures resulting in a lower voltage across the thermistor. the controller detects a fault once the thermistor voltage drops below v fault(otp_in) . options a and c latch ? off the controller after an overtemperature fault is detected. in options b and d the controller is re ? enabled once the fault is removed such that v fault increases above v fault(otp_out) and v cc reaches v cc(on) . figure 10 shows typical waveforms related to the latch option whereas figure 11 shows waveforms of the auto ? recovery option. an active clamp prevents the fault pin voltage from reaching the upper latch threshold if the pin is open. to reach the upper threshold, the external pull ? up current has to be higher than the pull ? down capability of the clamp (set by r fault(clamp) at v fault(clamp) ). the upper fault threshold is intended to be used for an overvoltage fault using a zener diode and a resistor in series from the auxiliary winding voltage, v aux . the controller is latched once v fault exceeds v fault(ovp) . the fault input signal is filtered to prevent noise from triggering the fault detectors. upper and lower fault detector blanking delays, t delay(fault_ovp) and t delay(fault_otp) are both typically 30 s. a fault is detected if the fault condition is asserted for a period longer than the blanking delay. a bypass capacitor is usually connected between the fault and gnd pins and it will take some time for v fault to reach its steady state value once i fault(otp) is enabled. therefore, a lower fault (i.e. overtemperature) is ignored during soft ? start. in options b and d, i fault(otp) remains enabled while the lower fault is present independent of v cc in order to provide temperature hysteresis. the controller can detect an upper ovp fault once v cc exceeds v cc(reset). the ovp fault detection remains active provided the device is not in psm. once the controller is latched, it is reset if a brown ? out condition is detected or if v cc is cycled down to its reset level, v cc(reset) . in the typical application these conditions occur only if the ac voltage is removed from the system. prior to reaching v cc(reset), v fault(clamp) is set at 0 v. figure 9. fault detection schematic v dd latch soft ? start end fault ? + blanking blanking ? + s r q vaux ntc thermistor auto ? restart control auto ? restart bo_ok reset line removal option hysteresis control v fault(clamp) r fault(clamp) v fault(otp) i fault(otp) v fault(ovp) t delay(fault_ovp) t delay(fault_otp)
ncp1937 http://onsemi.com 20 figure 10. latch ? off function timing diagram qdrv time otp fault flag otp fault detected t delay(fault_otp) v cc(off) v cc(on) v cc v fault v fault(clamp) v fault(otp) figure 11. otp auto ? recovery timing diagram qdrv time otp fault flag (otp fault ignored) otp fault is cleared otp fault detected t sstart t delay(fault_otp) v cc v cc(on) v cc(off) v fault v fault(clamp) v fault(otp_out) v fault(otp_in) v fault(otp)
ncp1937 http://onsemi.com 21 qr flyback valley lockout the ncp1937 integrates a quasi ? resonant (qr) flyback controller. the power switch turn ? off of a qr converter is determined by the peak current set by the feedback loop. the switch turn ? on is determined by the transformer demagnetization. the demagnetization is detected by monitoring the transformer auxiliary winding voltage. turning on the power switch once the transformer is demagnetized or reset reduces switching losses. once the transformer is demagnetized, the drain voltage starts ringing at a frequency determined by the transformer magnetizing inductance and the drain lump capacitance eventually settling at the input voltage. a qr controller takes advantage of the drain voltage ringing and turns on the power switch at the drain voltage minimum or ?valley? to reduce switching losses and electromagnetic interference (emi). the operating frequency of a traditional qr flyback controller is inversely proportional to the system load. that is, a load reduction increases the operating frequency. this tradionally requires a maximum frequency clamp to limit the operating frequency. this causes the controller to become unstable and jump (or hesitate) between two valleys generating audible noise. the ncp1937 incorporates a patent pending valley lockout circuitry to eliminate valley jumping. once a valley is selected, the controller stays locked in this valley until the output power changes significantly. like a traditional qr flyback controller, the frequency increases when the load decreases. once a higher valley is selected the frequency decreases very rapidly. it will continue to increase if the load is further reduced. this technique extends qr operation over a wider output power range while maintaining good efficiency and limiting the maximum operating frequency. figure 12 shows a qualitative frequency vs output power relationship. figure 13 shows the internal arrangement of the valley lockout circuitry. the decimal counter increases each time a valley is detected. the operating valley (1 st , 2 nd , 3 rd or 4 th ) is determined by the qfb voltage. as v qfb decreases or increases, the valley comparators toggle one after another to select the proper valley. the activation of an ?n? valley comparator blanks the ?n ? 1? or ?n+1? valley comparator output depending if v qfb decreases or increases, respectively. a valley is detected once v qzcd falls below the qr flyback demagnetization threshold, v qzcd(th) , typically 55 mv. the controller will switch once the valley is detected or increment the valley counter depending on qfb voltage. figure 12. valley lockout frequency vs. output power relationship
ncp1937 http://onsemi.com 22 figure 13. valley lockout detection circuitry internal schematic figure 14 shows the operating valley versus v qfb . once a valley is asserted by the valley selection circuitry, the controller is locked in this valley until v qfb decreases or increases such that v qfb reaches the next valley threshold. a decrease in output power causes the controller to switch from ?n? to ?n+1? valley until reaching the 4 th valley. a further reduction of output power causes the controller to enter the voltage control oscillator (vco) mode once v qfb falls below v hvcod . in vco mode the peak current is set as shown in figure 15. the operating frequency in vco mode is adjusted to deliver the required output power. a hysteresis between valleys provides noise immunity and helps stabilize the valley selection in case of small perturbations on v qfb . valley v qfb v qilim1 *k qfb v h2d v hvcoi v h3d v h4d v hvcod v h4i v h3i v h2i 4th 3rd 2nd 1st vco figure 14. selected operating valley vs. v qfb
ncp1937 http://onsemi.com 23 ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? ?????? peak current setpoint 2nd 3rd 4th vco mode qr mode skip v qfb v qilim1 i peak(vco) *v qilim1 v h2d v h3d v h4d v hvcod v qfb(th) fault v qilim1 *k qfb 1st valley v qskip figure 15. operating valley vs. v qfb figure 16 through figure 19 show drain voltage, v qfb and v qct simulation waveforms for a reduction in output power. the transitions between 2 nd to 3 rd , 3 rd to 4 th and 4 th valley to vco mode are observed without any instabilities or valley jumping. figure 16. operating mode transitions between 2 nd to 3 rd , 3 rd to 4 th and 4 th valley to vco mode ? ? 100 100 300 500 700 vdrain in volts plot1 1 400m 800m 1.20 1.60 2.00 feedback in volts plot2 2 3.64m 4.91m 6.18m 7.45m 8.72m time in seconds ? 1.00 1.00 3.00 5.00 7.00 vct in volts plot3 3
ncp1937 http://onsemi.com 24 figure 17. zoom 1: 2 nd to 3 rd valley transition ? 1 vdrain 2 feedback 3 vct ? 100 100 300 500 700 vdrain in volts plot1 1 1.75 1.85 1.95 2.05 2.15 feedback in volts plot2 2 3.70m 3.78m 3.86m 3.94m 4.02m time in seconds ? 2.00 0 2.00 4.00 6.00 vct in volts plot3 3 figure 18. zoom 2: 3 rd to 4 th valley transition 1 vdrain 2 feedback 3 vct ? 100 100 300 500 700 plot1 vdrain in volts 1 1.22 1.26 1.30 1.34 1.38 plot2 feedback in volts 2 5.90m 5.95m 6.00m 6.05m 6.11m time in seconds 0 1.00 2.00 3.00 4.00 t ilt vc n vo s 3 figure 19. zoom 3: 4 th valley to vco mode transition ? 1 vdrain 2 feedback 3 vct ? 100 100 300 500 700 vdrain in volts plot1 1 719m 819m 919m 1.02 1.12 feedback in volts 2 plot2 7.10m 7.21m 7.32m 7.43m 7.55m time in seconds 0 2.00 4.00 6.00 8.00 vct in volts 3 plot3
ncp1937 http://onsemi.com 25 vco mode the controller enters vco mode once v qfb falls below v hvcod and remains in vco until v qfb exceeds v hvcoi . in vco mode the peak current is set to v qilim1 *i peak(vco) and the operating frequency is linearly dependent on v qfb . the product of v qilim1 *i peak(vco) is typically 12.5%. a minimum frequency clamp, f vco(min) , typically 27 khz, prevents operation in the audible range. further reduction in output power causes the controller to enter skip operation. the minimum frequency clamp is only enabled when operating in vco mode. the vco mode operating frequency is set by the timing capacitor connected between the qct and gnd pins. this capacitor is charged with a constant current source, i qct , typically 20 a. the capacitor voltage, v qct , is compared to an internal voltage level, v f(qfb) , inversely proportional to v qfb the relationship between and v f(qfb) and v qfb is given by equation 6. v f (qfb) 5 2 v qfb (eq. 6) a drive pulse is generated once v qct exceeds v f(qfb) followed by the immediate discharge of the timing capacitor. the timing capacitor is also discharged once the minimum frequency clamp is reached. figure 20 shows simulation waveforms of v f(qfb) , v qdrv and output current while operating in vco mode. 0 200m 400m 600m 800m 1 ? 1.00 1.00 3.00 5.00 7.00 2 3 7.57m 7.78m 7.99m 8.20m 8.40m time in seconds ? 10.0 0 10.0 20.0 30.0 5 v qdrv v f(qfb) i out figure 20. vco mode operating waveforms v qct
ncp1937 http://onsemi.com 26 flyback timeout in case of extremely damped oscillations, the qzcd comparator may be unable to detect the valleys. in this condition, drive pulses will stop waiting for the next valley or zcd event. the ncp1937 ensures continued operation by incorporating a maximum timeout period after the last demagnetization detection. the timeout signal is a substitute for the zcd signal for the valley counter. figure 21 shows the timeout period generator circuit schematic. the steady state timeout period, t q(tout2) , is set at 6 s to limit the frequency step. during startup, the voltage offset added by the overpower compensation diode, d opp , prevents the qzcd comparator from accurately detecting the valleys. in this condition, the steady state timeout period will be shorter than the inductor demagnetization period causing continuous current mode (ccm) operation. ccm operation lasts for a few cycles until the voltage on the qzcd pin is high enough to detect the valleys. a longer timeout period, t q(tout1) , (typically 100 s) is set during soft ? start to limit ccm operation. figure 22 and figure 23 show the timeout period generator related waveforms. figure 21. timeout period generator circuit schematic
ncp1937 http://onsemi.com 27 4 3 14 12 15 16 17 the 3rd valley is validated the 3rd valley is not detected by the qzcd comparator timeout adds a pulse to account for the missing 3 rd valley the 2 nd valley is detected by the qzcd comparator figure 22. timeout operation with a missing 3 rd valley v qzcd(th) v qzcd 2nd, 3rd qzcd comparator output timeout clk high low high low high low high low 4 3 14 18 15 16 17 timeout adds 2 pulses to account for the missing 3 rd and 4 th valleys the 4 th valley is validated figure 23. timeout operation with missing 3 rd and 4 th valleys v qzcd(th) v qzcd 3rd, 4th qzcd comparator output timeout clk high low high low high low high low
ncp1937 http://onsemi.com 28 qr flyback current sense and overload the power switch on time is modulated by comparing a ramp proportional to the switch current to v qfb /k qfb using the pwm comparator. the switch current is sensed across a current sense resistor, r sense, and the resulting voltage is applied to the qcs pin. the current signal is blanked by a leading edge blanking (leb) circuit. the blanking period eliminates the leading edge spike and high frequency noise during the switch turn ? on event. the leb period, t qcs(leb1) , is typically 275 ns. the drive pulse terminates once the current sense signal exceeds v qfb /k qfb . the maximum peak current comparator compares the current sense signal to a reference voltage to limit the maximum peak current of the system. the maximum peak current reference voltage, v qilim1 , is typically 0.8 v. the maximum peak current setpoint is reduced by the overpower compensation circuitry. an overload condition causes the output of the maximum peak current comparator to transition high and enable the overload timer. figure 24 shows the implementation of the current sensing circuitry. figure 24. current sensing circuitry schematic pwm comparator peak current comparator leb fault over current comparator qfb qcs leb csstop qdrv counter reset count disable qdrv count up count down overload timer + ? + ? + ? + + v dd v qilim2 v qzcd v qilim1 i qcs v qzcd v dd t qcs(leb1) t qcs(leb2) skip /k qfb v qskip v qfb i qfb r qfb in_psm i peak(vco) = k qcs(vco) t qovld the overload timer integrates the duration of the overload fault. that is, the timer count increases while the fault is present and reduces its count once it is removed. the overload timer duration, t qovld , is typically 80 ms. if both the pwm and maximum peak current comparators toggle at the same time, the pwm comparator takes precedence and the overload timer counts down. the controller can latch (options c and d) or allow for auto ? recovery (options a and b) once the overload timer expires. auto ? recovery requires a v cc triple hiccup before the controller restarts. figure 25 and figure 26 show operating waveforms for latched and auto ? recovery overload conditions.
ncp1937 http://onsemi.com 29 figure 25. latched overload operation figure 26. auto ? recovery overload operation
ncp1937 http://onsemi.com 30 a severe overload fault like a secondary side winding short ? circuit causes the switch current to increase very rapidly during the on ? time. the current sense signal significantly exceeds v qilim1 . but, because the current sense signal is blanked by the leb circuit during the switch turn on, the system current can get extremely high causing system damage. the ncp1937 protects against this fault by adding an additional comparator, fault overcurrent comparator. the current sense signal is blanked with a shorter leb duration, t qcs(leb2) , typically 120 ns, before applying it to the fault overcurrent comparator. the voltage threshold of the comparator, v qilim2 , typically 1.2 v, is set 50% higher than v qilim1 , to avoid interference with normal operation. four consecutive faults detected by the fault overcurrent comparator causes the controller to enter latch mode. the count to 4 provides noise immunity during surge testing. the counter is reset each time a qdrv pulse occurs without activating the fault overcurrent comparator. a 1 a (typically) pull ? up current source, i qcs , pulls up the qcs pin to disable the controller if the pin is left open. qr flyback soft ? start soft ? start is achieved by ramping up an internal reference, v sstart , and comparing it to current sense signal. v sstart ramps up from 0 v once the controller powers up. the soft ? start duration, t sstart , is typically 4 ms. during soft ? start the timeout duration is extended and the lower latch or otp comparator signal (typically for overtemperature) is blanked. soft ? start ends once v sstart exceeds the peak current sense signal threshold. qr flyback overpower compensation the input voltage of the qr flyback stage varies with the line voltage and operating mode of the pfc converter. at low line the pfc bulk voltage is 250 v and at high line it is 400 v. in addition, the pfc can be disabled at light loads to reduce input power at which point the pfc bulk voltage is set by the rectified peak line voltage. an integrated overpower circuit provides a relative constant output power across pfc bulk voltage, v bulk . it also reduces the variation on v qfb during the pfc stage enable or disable transitions. figure 27 shows the circuit schematic for the overpower detector. the auxiliary winding voltage during the power switch on time is a reflection of the input voltage scaled by the primary to auxiliary winding turns ratio, n p,aux , as shown in figure 28. figure 27. overpower compensation circuit schematic qzcd qzcd comparator + qcs leb other faults disable qdrv pwm comparator qfb peak current comparator + ? + ? /4 + + ? v qzcd(th) v qilim1 k qcs(vco) t qcs(leb1) d opp l aux r qczd r oppu r oppl figure 28. auxiliary winding voltage waveform
ncp1937 http://onsemi.com 31 overpower compensation is achieved by scaling down the on ? time reflected voltage and applying it to the qzcd pin. the voltage is scaled down using r oppu and r oppl . the negative voltage applied to the pin is referred to as v opp . the internal current setpoint is the sum of v opp and peak current sense threshold, v qilim1 . v opp is also subtracted from v qfb to compensate for the pwm comparator delay and improve the pfc on/off accuracy. the current setpoint is calculated using equation 7. for example, a v opp of ? 0.15 v results in a current setpoint of 0.65 v. current setpoint v qilim1 v opp (eq. 7) to ensure optimal zero ? crossing detection, a diode is needed to bypass r oppu during the off ? time. equation 8 is used to calculate r oppu and r oppl . r qzcd r oppu r oppl n p,aux v bulk v opp v opp (eq. 8) r oppu is selected once a value is chosen for r oppl . r oppl is selected large enough such that enough voltage is available for the zero crossing detection during the off ? time. it is recommended to have at least 8 v applied on the qzcd pin for good detection. the maximum voltage is internally clamped to v cc . the off ? time voltage on the qzcd is given by equation 9. v qzcd r oppl r qzcd r oppl v aux v f (eq. 9) where v aux is the voltage across the auxiliary winding and v f is the d opp forward voltage drop. the ratio between r qzcd and r oppl is given by equation 10. it is obtained combining equations 8 and 9. r qzcd r oppl v aux v f v qzcd v qzd (eq. 10) a design example is shown below: system parameters: v aux = 18 v v f = 0.6 v n p,aux = 0.18 the ratio between r qzcd and r oppl is calculated using equation 10 for a minimum v qzcd of 8 v. r qzcd r oppl 18 0.6 8 8 1.2 r qzcd is arbitrarily set to 1 k . r oppl is also set to 1 k because the ratio between the resistors is close to 1. the ncp1937 maximum overpower compensation or peak current setpoint reduction is 31.25% for a v opp of ? 250 mv. we will use this value for the following example: substituting values in equation 8 and solving for r oppu we obtain, r qzcd r oppu r oppl 0.18 370 ( ? 0.25) ( ? 0.25) 271 r oppu 271 r oppl r qzcd r oppu 271 1k 1k 270 k power factor correction the pfc stage operates in critical conduction mode (crm). in crm, the pfc inductor current, i l (t) reaches zero at the end of each switch cycle. figure 29 shows the pfc inductor current while operating in crm. the average input current, i in (t), is in phase with the ac line voltage, v in (t), to achieve power factor correction. figure 29. inductor current in crm high power factor is achieved in crm by maintaining a constant on time (t on ) for a given rms input voltage (v ac(rms) ) and load condition. equation 11 shows the relationship between on time and system operating conditions. t on 2 p out l v ac(rms) 2 (eq. 11) where p out is the output power, l is the pfc choke inductance and is the system efficiency. pfc feedback the pfc feedback circuitry is shown in figure 30. a transconductance error amplifier regulates the pfc output voltage, v bulk , by comparing the pfc feedback signal to an internal reference voltage, v pref . the feedback signal is applied to the inverting input and the reference is connected to the non ? inverting input of the error amplifier. a resistor divider consisting of r1 and r2 scales down v bulk to generate the pfc feedback signal. v pref is trimmed during manufacturing to achieve an accuracy of 2%. the pfc stage is disabled at light loads to reduce input power. the ncp1937 integrates a 700 v switch, pfc fb switch, between the pfbhv and pfblv pins. the pfc fb switch is in series between r1 and r2 to disconnect the resistors and reduce input power when the pfc stage is disabled.
ncp1937 http://onsemi.com 32 figure 30. pfc regulation circuit schematic error amplifier + ? pfbhv stop latchoff pilim1, pilim2 pfcdrv s r q dominant reset latch enable pfc delay pfblv pfc faults and disable signals r1 r2 pfc fb switch pfc uvp comparator high clamp low clamp puvp disable pfc puvp pcontrol + ? v bulk v dd v pref v pfb(disable) q t penable the maximum on resistance of the pfc fb switch, r pfbswitch(on) , is 10 k . because the pfc fb switch is in series with r1 and r1?s value is several orders of magnitudes larger, the switch introduces minimum error on the regulation level. the off state leakage current of the pfc fb switch, i pfbswitch(off) , is less than 3 a. the ncp1937 safely disables the controller if the pfblv pin is grounded. a short pin detector disables the controller if v pfblv is below the disable threshold, v pfb(disable) , typically 0.3 v. if the pfblv pin is open, the pfc fb switch will raise v pfblv above the overvoltage threshold and disable the controller. equation 12 shows the relationship between the pfc output voltage, the pfc reference threshold, r1 and r2. v pfc v pref(xl) r1 r2 r2 (eq. 12) pfc error amplifier a transconductance amplifier has a voltage ? to ? current gain, g m . that is, the amplifier?s output current is controlled by the differential input voltage. the ncp1937 amplifier has a typical g m of 200 s. the pcontrol pin provides access to the amplifier output for compensation. the compensation network is ground referenced allowing the pfc feedback signal to be used to detect an overvoltage condition. the compensation network on the pcontrol pin is selected to filter the bulk voltage ripple such that a constant control voltage is maintained across the ac line cycle. a capacitor between the pcontrol pin and ground sets a pole. a pole at or below 20 hz is enough to filter the ripple voltage for a 50 and 60 hz system. the low frequency pole, f p , of the system is calculated using equation 13. f p gm 2 c pcontrol (eq. 13) where, c pcontrol is the capacitor on the pcontrol pin to ground. the output of the error amplifier is held low when the pfc is disabled by means of an internal pull ? down transistor. the pull down transistor is disabled once the pfc stage is enabled. an internal voltage clamp is then enabled to quickly raise v pcontrol to its minimum voltage, v pclamp(lower) . pfc on ? time the pfc on time is controlled by v pcontrol . the pfc on ? time comparator terminates the drive pulse once the pfc on ? time ramp voltage plus offset exceeds v pcontrol . the ramp is generated by charging an internal timing capacitor, c pct , with a constant current source, i pct . the capacitor ramp is level shifted to achieve 0 duty ratio (stop drive pulses) at the minimum v pcontrol . v pcontrol is proportional to the output power and it is fixed for a given rms line voltage and output load, satisfying equation 11. lower and upper voltage clamps limit the excursion of v pcontrol . the maximum on ? time, t on(max) , occurs when v pcontrol is at its maximum value, v pcontrol(max) . the pfc drive pulses are inhibited once v pcontrol is below its minimum value, v pcontrol(min) . the maximum pfc on ? time in the ncp1937 is set internally. the maximum on time at low line is typically 15 s.
ncp1937 http://onsemi.com 33 pfc transient response the pfc bandwidth is set low enough to achieve good power factor . a low bandwidth system is slow and fast load transients can result in large output voltage excursions. the ncp1937 incorporates dedicated circuitry to help mantain regulation of the output voltage independent of load transients. an undervoltage detector monitors v bulk and prevents it from dropping below from its regulation level. once the ratio between v pfblv and v pref(xl) exceeds k low(pfcxl) , typically 5.5%, a pull ? up current source on the pcontrol pin, i pcontrol(boost) , is enabled to speed up the charge of the compensation capacitor(s). this results in an increased on ? time and thus output power. i pcontrol(boost) is typically 240 a. the boost current source is disabled once the ratio between v pfblv and v pref(xl) drops below k low(pfcxl) , typically 4%. the boost current source becomes active as soon as the pfc is enabled. coupled with the lower control clamp, the current provided by the boost current source assists in rapidly bringing v pcontrol to its set point to allow the bulk voltage to quickly reach regulation. achieving regulation is detected by monitoring the error amplifier output current. the error amplifier output current drops to zero once the pfc output voltage reaches the target regulation level. the maximum pfc output voltage is limited by the overvoltage protection circuitry. the ncp1937 incorporates both soft and hard overvoltage protection. the hard overvoltage protection function immediately terminates and prevents further pfc drive pulses when v pfblv exceeds the hard ? ovp level, v pref(xl) * k povp(xl). soft ? ovp reduces the on ? time proportional to the delta between v pfblv and the hard ? ovp level. soft ? ovp is enabled once the delta, povp(xl) , between v pfblv and the hard ? ovp level, is between 20 and 55 mv. figure 31 shows the circuit schematic of the boost and soft ? ovp circuits. figure 31. boost and soft ? ovp circuit schematics during power up, v pcontrol exceeds the regulation level due to the system?s inherently low bandwidth. this causes the bulk voltage to rapidly increase and exceed its regulation. the on time starts to decrease when soft ? ovp is activated. once the bulk voltage decreases to its regulation level the pfc on time is no longer controlled by the soft ? ovp circuitry. pfc current sense and zero current detection the ncp1937 uses a novel architecture combining the pfc current sense and zero current detectors (zcd) in a single input terminal. figure 32 shows the circuit schematic of the current sense and zcd detectors.
ncp1937 http://onsemi.com 34 figure 32. pfc current sense and zcd detectors schematic to pdrv set frequency clamp timer clk dq zcd comparator pdrv reset + ? pfc timeout reset pdrv pcs/pzcd pfc inductor pfc switch pdrv leb1 current limit comparator short circuit detector leb2 latchoff boost diode counter count reset pilim2 r s q dominant reset latch other latching faults pfc boost diode + ? zcd_lat pilim1 pdrv pdrv clk dq r vdd pdrvrst pilim2 r pzcd r pcs r psense v zcd q q t pcs(leb2) t pcs(leb1) v pilim2 v pilim1 q t pfc(out) t pfc(off) timer pfc current sense the pfc switch current is sensed across a sense resistor, r psense , and the resulting voltage ramp is applied to the pcs/pzcd pin. the current signal is blanked by a leading edge blanking (leb) circuit. the blanking period eliminates the leading edge spike and high frequency noise during the switch turn ? on event. the leb period, t pcs(leb1) , is typically 325 ns. the current limit comparator disables the pfc driver once the current sense signal exceeds the pfc current sense reference, v pilim1 , typically 0.5 v. a severe overload fault like a pfc boost diode short circuit causes the switch current to increase very rapidly during the on ? time. the current sense signal significantly exceeds v pilim1 . but, because the current sense signal is blanked by the leb circuit during the switch turn on, the system current can get extremely high causing system damage. the ncp1937 protects against this fault by adding an additional comparator, pfc short circuit comparator. the current sense signal is blanked with a shorter leb duration, t pcs(leb2) , typically 175 ns, before applying it to the pfc short circuit comparator. the voltage threshold of the comparator, v pilim2 , typically 1.25 v, is set 250% higher than v pilim1 , to avoid interference with normal operation. four consecutive faults detected by the short circuit comparator causes the controller to enter latch mode. the count to 4 provides noise immunity during surge testing. the counter is reset each time a pdrv pulse occurs without activating the short circuit comparator. the pfc watchdog timer duration increases to t pfc(off2) (typically 1 ms) when a v pilim2 fault is detected independent of the pfc zcd state. pfc zero current detection the off ? time in a crm pfc topology varies with the instantaneous line voltage and is adjusted every switching cycle to allow the inductor current to reach zero before the next switching cycle begins. the inductor is demagnetized once its current reaches zero. once the inductor is demagnetized the drain voltage of the pfc switch begins to drop. the inductor demagnetization is detected by sensing the voltage across the inductor using an auxiliary winding. this winding is commonly known as a zero crossing detector (zcd) winding. this winding provides a scaled version of the inductor voltage. figure 33 shows the zcd winding arrangement.
ncp1937 http://onsemi.com 35 figure 33. zcd winding implementation the zcd voltage, v zcd , is positive while the pfc switch is off and current flows through the pfc inductor. v zcd drops to and rings around zero volts once the inductor is demagnetized. the next switching cycle begins once a negative transition is detected on the pcs/pzcd pin. a positive transition (corresponding to the pfc switch turn off) arms the zcd detector to prevent false triggering. the arming of the zcd detector, v pzcd(rising) , is typically 0.75 v (v pcs/pzcd increasing). the trigger threshold, v pzcd(falling) , is typically 0.25 v (v pcs/pzcd decreasing). the pcs/pzcd pin is internally clamped to 5 v with a zener diode and a 2 k resistor. a resistor in series with the pcs/pzcd pin is required to limit the current into pin. the zener diode also prevents the voltage from going below ground. figure 34 shows typical zcd waveforms. during startup there are no zcd transitions to set the pfc pwm latch and generate a pdrv pulse. a watchdog timer, t pfc(off1) , starts the drive pulses in the absence of zcd transitions. its duration is typically 200 s. the timer is also useful if the line voltage transitions from low line to high line and while operating at light load because the amplitude of the zcd signal may be too small to cross the zcd arming threshold. the watchdog timer is reset at the beginning of a pfc drive pulse. it is disabled during a pfc hard overvoltage and feedback input short circuit condition. figure 34. zcd winding waveforms the watchdog timer duration increases to t pfc(off2) , typically 1 ms, when a v pilim2 fault is detected. pfc frequency clamp the pfc operating frequency naturally increases when the line voltage gets near to zero due to the reduced demagnetization time or when the pfc is operating at light loads. a maximum frequency clamp, f clamp(pfc) , limits the pfc frequency to improve efficiency and facilitate compliance with emi requirements. the ncp1937 has options for pfc frequency clamp values of 131 khz or 250 khz. the pdrv pulse is blanked until the frequency clamp timer expires. once expired, the controller waits for the next zcd transition to initiate pdrv. this ensures valley switching to reduce switching losses. a timeout timer, t p(tout) , starts the next pdrv pulse in the absence of a zcd transition. the timeout timer duration is typically 10 s. the timer is reset at every zcd event. figure 35 shows the block diagram of the pfc frequency clamp. figure 35. pfc frequency clamp schematic to pdrv set frequency clamp timer clk d q zcd comparator pdrv reset + ? pfc timeout reset pdrv pcs/pzcd pfc inductor pfc switch pdrv pfc boost diode zcd_lat clk d q r vdd pilim2 r pzcd r pcs r psense v zcd q q t pfc(out) t pfc(off) timer
ncp1937 http://onsemi.com 36 pfc enable & disable in some applications it is desired to disable the pfc at lighter loads to increase the overall system efficiency. the ncp1937 integrates a novel architecture that allows the user to program the pfc disable threshold based on the percentage of qr output power. the pfc enable circuitry is inactive until the qr flyback soft start period has ended. a voltage to current (v ? i) converter generates a current proportional to v qfb . this current is pulse width modulated by the demagnetization time of the flyback controller to generate a current, i ponoff , proportional to the output power. an external resistor, r ponoff , between the ponoff and gnd pins generate a voltage proportional to the output power. this resistor is used to scale the output power signal. a capacitor, c ponoff , in parallel with r ponoff is required to average the signal on this pin. a good compromise between voltage ripple and speed is achieved by setting the time constant of c ponoff and r ponoff to 160 s. the ponoff pin voltage, v ponoff , is compared to an internal reference, v poff (typically 2 v) to disable the pfc stage. the pfc disable point is typically set between 25 and 50% or between 50 and 75% of the maximum system load. these setpoints provide the best system efficiency across low line and high line. once v ponoff decreases below v poff , the pfc disable timer, t pdisable , is enabled. the ncp1937 has options for 500 ms, 4 s, or 13 s pfc disable timer. the pfc stage is disabled once the timer expires. the pfc stage is enabled once v ponoff exceeds v poff by v ponhys for a period longer than the pfc enable filter, t penable(filter) , typically 100 s. a shorter delay for the pfc enable threshold is used to reduce the bulk capacitor requirements during a step load response. figure 36 shows the block diagram of the pfc disable circuit. figure 36. pfc on/off control circuitry disable pfc ponoff reset pfc disable timer qfb demag time calculator pfc enable timer dominant reset latch s r q qdrv enable ponoff comparator soft ? start complete qzcd ? + + ? hysteresis control v poff c ponoff rc ponoff i ponoff v to i converter release pcontrol turn on pfc fb switch q t penable t pdisable t penable(filter) filter delay pfc skip the pfc stage incorporates skip cycle operation at light loads to reduce input power. skip operation disables the pfc stage if the pcontrol voltage decreases below the skip threshold. the skip threshold voltage is typically 25 mv ( v pskip ) above the pcontrol lower voltage clamp, v clamp(lower) . the pfc stage is enabled once v pcontrol increases above the skip threshold by the skip hysteresis, v pskip(hys) . pfc skip is disabled during any initial pfc startup and when the pfc is in a uvp. skip operation will become active after the pfc has reached regulation. pfc and flyback drivers the ncp1937 maximum supply voltage, v cc(max) , is 30 v. typical high voltage mosfets have a maximum gate voltage rating of 20 v. both the pfc and flyback drivers incorporate an active voltage clamp to limit the gate voltage on the external mosfets. the pfc and flyback voltage clamps, v pdrv(high) and v qdrv(high) , are typically 12 v with a maximum limit of 14 v. auto recovery the controller is disabled and enters ?triple ? hiccup? mode if v cc drops below v cc(off) . the controller will also enter ?triple ? hiccup? mode if an overload fault is detected on the non ? latching version. a hiccup consists of v cc falling down to v cc(off) and charging up to v cc(on) . the controller needs to complete 3 hiccups before restarting. temperature shutdown an internal thermal shutdown circuit monitors the junction temperature of the ic. the controller is disabled if the junction temperature exceeds the thermal shutdown threshold, t shdn , typically 150 c. a continuous v cc hiccup is i nitiated after a thermal shutdown fault is detected. the controller restarts at the next v cc(on) once the ic temperature drops below below t shdn by the thermal shutdown hysteresis, t shdn(hys) , typically 40 c. the thermal shutdown fault is also cleared if v cc drops below v cc(reset) , a brown ? out fault is detected or if the line voltage is removed. a new power up sequences commences at the next v cc(on) once all the faults are removed.
ncp1937 http://onsemi.com 37 package dimensions ???? ???? case 751bs ? 01 issue o 6.30 17x 0.53 17x 0.85 1.00 dimensions: millimeters 1 pitch 20 10 11 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* notes: 1. dimensioning and tolerancing per asme y14.5m, 1994. 2. controlling dimension: millimeters. 3. dimension b does not include dambar protrusion. allowable protrusion shall be 0.10 total in excess of the b dimension. dimension b applies to the flat portion of the lead and shall be measured between 0.13 and 0.25 from the tip. 4. dimensions d and e1 do not include mold flash, protrusions, or gate burrs but do include mold mismatch. mold flash, protrusions, or gate burrs shall not exceed 0.15mm per side. dimensions d and e1 are determined at datum h. 5. datums a and b are to be determined at datum h. 6. a1 is defined as the vertical distance from the seat- ing plane to the lowest point on the package body. 7. chamfer feature is optional. if not present, then a pin one identifier must be located in this area. 110 20 11 seating plane l h note 7 a1 a dim min max millimeters a --- 1.70 b 0.31 0.51 l 0.40 0.85 d 9.90 bsc c 0.10 0.25 a1 0.00 0.20 m 0 8 h 0.25 0.50 b 17x a b c e 6.00 bsc e1 3.90 bsc e 1.00 bsc l2 0.25 bsc e e1 d d a-b m 0.25 d c 0.20 c recommended note 4 note 4 note 5 note 5 e 0.10 c a-b 0.10 c a-b note 3 0.10 c 0.10 c m c h detail a h seating plane c l2 detail a on semiconductor and are registered trademarks of semiconductor co mponents industries, llc (scillc). scillc owns the rights to a numb er of patents, trademarks, copyrights, trade secrets, and other intellectual property. a list ing of scillc?s product/patent coverage may be accessed at ww w.onsemi.com/site/pdf/patent ? marking.pdf. scillc reserves the right to make changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and s pecifically disclaims any and all liability, including without limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/ or specifications can and do vary in different applications and actual performance may vary over time. all operating parame ters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the right s of others. scillc products are not designed, intended, or a uthorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in whic h the failure of the scillc product could create a situation where personal injury or death may occur. should buyer purchase or us e scillc products for any such unintended or unauthorized appli cation, buyer shall indemnify and hold scillc and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unin tended or unauthorized use, even if such claim alleges that scil lc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyrig ht laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5817 ? 1050 ncp1937/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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